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May 1997
ML4823 High Frequency Power Supply Controller
GENERAL DESCRIPTION
The ML4823 High Frequency PWM Controller is an IC controller optimized for use in Switch Mode Power Supply designs running at frequencies to 1MHz. Propagation delays are minimal through the comparators and logic for reliable high frequency operation while slew rate and bandwidth are maximized on the error amplifier. This controller is designed for single-ended applications using voltage or current mode and provides for input voltage feed forward. A 1V threshold current limit comparator provides cycleby-cycle current limit and exceeding a 1.4V threshold initiates a soft-start cycle. The soft start pin doubles as a maximum duty cycle clamp. All logic is fully latched to provide jitter-free operation and prevent multiple pulsing. An under-voltage lockout circuit with 800mV of hysteresis assures low startup current and drives the outputs low during fault conditions. This controller is an improved second source for the UC3823 controller; however, the ML4823 includes features not found on the 3823. These features are set in italics.
FEATURES
s s s s s s s s s s s s s
Practical operation at switching frequencies to 1.0MHz High current (2A peak) totem pole output Wide bandwidth error amplifier Fully latched logic with double pulse suppression Pulse-by-pulse current limiting Soft start and max. duty cycle control Under voltage lockout with hysteresis 5.1V trimmed bandgap reference Low start-up current (1.1mA) Pin compatible improved replacement for UC3823 Fast shut down path from current limit to output Soft start latch ensures full soft start cycle Outputs pull low for undervoltage lockout
BLOCK DIAGRAM
5 6 RT CT OSC
(Pin Configuration Shown for 16-Pin Version)
CLOCK OUT
4
7 3
RAMP E/A OUT
1.25V +
R + COMP - S Q
2 1
NI INV
+ ERROR AMP -
V+
POWER VC OUTPUT POWER GND - + - + ENABLE VREF VREF GEN - + 9V INTERNAL BIAS VCC SIGNAL GND 4V
13 14 12
8
SOFT START ILIM REF ILIM/S.D. - + R + - Q S UNDER VOLTAGE LOCKOUT 5.1V
11 9
1V
5.1V VREF
16
1.4V
15
10
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ML4823
PIN CONFIGURATION
ML4823 16-PIN DIP (P16) 16-PIN SOIC (S16W)
INV NI E/A OUT CLOCK RT CT RAMP SS
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
ML4823 20-PIN PLCC (Q20)
5.1V REF
20
5.1V REF VCC OUTPUT VC PWR GND ILIM REF GND ILIM/S.D.
E/A OUT CLOCK NC RT CT 4 5 6 7 8
3
2
1
19 18 17 16 15 14 OUTPUT VC NC PWR GND ILIM REF
TOP VIEW
9
10
11
12
13
ILIM/S.D.
RAMP
SS
TOP VIEW
PIN DESCRIPTION
PIN NAME
(Pin Numbers in Parentheses are for PLCC Version)
PIN NAME FUNCTION
FUNCTION
1 (2) 2 (3) 3 (4) 4 (5) 5 (7)
INV NI
Inverting input to error amp. Non-inverting input to error amp.
9 (12) ILIM/S.D. 10 (13) GND 11 (14) ILIM REF
Current limit sense pin. Normally connected to current sense resistor. Analog signal ground. Reference input for cycle-by-cycle current limit comparator.
E/A OUT Output of error amplifier and input to main comparator. CLOCK RT Oscillator output. Timing resistor for oscillator -- sets charging current for oscillator timing capacitor (pin 6). Timing capacitor for oscillator. Non-inverting input to main comparator. Connected to CT for Voltage mode operation or to current sense resistor for current mode. Normally connected to soft start capacitor.
12 (15) PWR GND Return for the high current totem pole output. 13 (17) VC 14 (18) OUT B 15 (19) VCC 16 (20) 5.1V REF Positive supply for the high current totem pole output. High current totem pole output. Positive supply for the IC. Buffered output for the 5.1V voltage reference.
6 (8) 7 (9)
CT RAMP
8 (10)
SS
2
GND
NC
VCC
INV
NC
NI
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ML4823
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Supply Voltage (VC, VCC) ........................................... 30V OUTPUT Current, Source or Sink DC ....................................................................... 0.5A Pulse (0.5s) ......................................................... 2.0A Analog Inputs (INV, NI, RAMP, SS, ILIM) .................. GND -0.3V to 6V CLOCK OUTPUT Current ...................................... -5mA F/A OUT Current ...................................................... 5mA SOFT START Sink Current ....................................... 20mA RT Charging Current ............................................... -5mA Junction Temperature ............................................ 125C Storage Temperature Range ..................... -65C to 150C Lead Temperature (Soldering 10 sec.) .................... 260C Thermal Resistance (JA) Plastic DIP ....................................................... 80C/W Plastic SOIC................................................... 105C/W Plastic Chip Carrier (PLCC) .............................. 78C/W
OPERATING CONDITIONS
Temperature Range ML4823C .................................................. 0C to 70C ML4823I ................................................ -40C to 85C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, RT = 3.65k, CT = 1000pF, TA = Operating Temperature Range, VCC = 15V. (Note 1)
PARAMETER OSCILLATOR Initial Accuracy Voltage Stability Temperature Stability Total Variation Clock Out High Clock Out Low Ramp Peak Ramp Valley Ramp Valley to Peak REFERENCE Output Voltage Line Regulation Load Regulation Temperature Stability Total Variation Output Noise Voltage Long Term Stability Short Circuit Current ERROR AMPLIFIER Input Offset Voltage Input Bias Current Input Offset Current Open Loop Gain 1 VO 4V 50 0.6 0.1 95 30 3 1 mV A A dB TJ = 25C, IO = 1mA 10V VCC 30V 1mA IO 10mA -40C TJ 150C, Line, load, temp. 10Hz to 10kHz TJ = 125C, 1000 hrs, VREF = 0V -15 4.975 50 5 -50 25 -100 5.025 5.10 2 5 0.2 5.175 20 20 0.4 5.225 V mV mV % V V mV mA 2.6 0.7 1.6 Line, temp. 340 3.9 4.5 2.3 2.8 1.0 1.8 2.9 3.0 1.25 2.0 TJ = 25C, 10V VCC 30V, 360 400 0.2 5 460 440 2 kHz % % kHz V V V V V CONDITIONS MIN TYP MAX UNITS
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ML4823
ELECTRICAL CHARACTERISTICS
PARAMETER ERROR AMPLIFIER (Continued) CMRR PSRR Output Sink Current Output Source Current Output High Voltage Output Low Voltage Unity Gain Bandwidth Slew Rate PWM COMPARATOR RAMP Bias Current Duty Cycle Range E/A OUT Zero DC Threshold Delay to Output SOFT START Charge Current Discharge Current CURRENT LIMIT/SHUTDOWN ILIM Bias Current Current Limit Offset ILIM REF Common Mode Range Shutdown Threshold Delay to Output OUTPUT Output Low Level IOUT = 20mA IOUT = 200mA Output High Level IOUT = -20mA IOUT = -200mA Collector Leakage Rise/Fall Time UNDER VOLTAGE LOCKOUT Start Threshold UVLO Hysteresis SUPPLY Start Up Current ICC
Note 1:
(Continued)
CONDITIONS MIN TYP MAX UNITS
1.5 VCC 5.5V 10 VCC 30V VE/A OUT = 1V VE/A OUT = 4V IE/A OUT = -0.5mA IE/A OUT = 1mA
50 70 1 -0.5 4.0 0 3 6
80 100 2.5 -1.3 4.7 0.5 5.5 12 5.0 1.0
dB dB mA mA V V MHz V/s
VRAMP = 0V 0 VRAMP = 0V 1.1
-1
-5 80
A % V
1.25 50 80
ns
VSOFT START = 0.5V VSOFT START = 1V 0V ILIM 4V ILIM REF = 1.1V
3 1
9
20
A mA
10 0 1.0 1.25 1.40 50 15 1.25 1.55 80
A mV V V ns
0.25 1.2 12.8 12.0 13.5 13.0 100 30
0.40 2.2
V V V V
VC = 30V CL = 1000pF 8.8 0.4
500 60
A ns
9.2 0.8
9.7 1.2
V V
VCC = 8V INV, RANP, ILIM = 0V NI = 1V
1.1 22
2.5 33
mA mA
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
4
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ML4823
FUNCTIONAL DESCRIPTION
OSCILLATOR The ML4823 oscillator charges the external capacitor (CT) with a current (ISET) equal to 3/RSET. When the capacitor voltage reaches the upper threshold (Ramp Peak), the comparator changes state and the capacitor discharges to the lower threshold (Ramp Valley) through Q1. While the capacitor is discharging, Q2 provides a high pulse. The oscillator period can be described by the following relationship: TOSC = TRAMP + TDEADTIME where: TRAMP = C (Ramp Valley to Peak)/ISET and: TDEADTIME = C (Ramp Valley to Peak)/IQ1
ISET RT RT 3V 5.1V ISET
CT IQ1 Q1
+ -
160
Q2 CLOCK OUT
140
1.0nF
TD (ns)
400A
120
100 470pF
CLOCK OUT
80 10k
100k FREQ (Hz)
1M
TD RAMP PEAK CT RAMP VALLEY
Figure 3. Oscillator Deadtime vs Frequency
Figure 1. Oscillator Block Diagram
100k 100nF 47nF 22nF
30 25 20
RT (OHMS)
10nF 10k 4.7nF 2.2nF 1nF 470pF 1k 0.1k 1k 10k 100k 1M 10M
TD (s)
15 10
5
0 0.47
1.0
2.2
4.7
10.0
22
47
100
FREQ (Hz)
CT (nF)
Figure 2. Oscillator Timing Resistance vs Frequency
Figure 4. Oscillator Deadtime vs CT (3ky - RT - 100ky) 5
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ML4823
ERROR AMPLIFIER The ML4823 error amplifier is a 5.5MHz bandwidth 12V/s slew rate op-amp with provision for limiting the positive output voltage swing (Output Inhibit line) for ease in implementing the soft start function.
100
80
60 GAIN
5
40
4 VIN
20
(V)
3 VOUT 2
0 -20
0 0 -90
1 0 0.2 0.4 0.6 0.8 1.0
100
1K
10K 100K
1M
-180 10M 100M
TIME (s)
FREQ (Hz)
Figure 5. Unity Gain Slew Rate OUTPUT DRIVER STAGE The ML4823 Output Driver is a 2A peak output high speed totem pole circuit designed to quickly switch the gates of capacitive loads, such as power MOSFET transistors.
VCC POWER VC Q2 OUT
Figure 6. Open Loop Frequency Response
0.2 IL (A) 0
TOUT (V)
15
-0.2
10
Q1 POWER GND
5
0
0
40
80
120
160
200
TIME (ns)
Figure 7. Simplified Schematic
3
Figure 9. Rise/Fall Time (CL = 1000pF)
2 IL (A) 0
2
VSAT (V)
TOUT (V)
SOURCE
15
-2
10
1
5
SINK
0
0
0
100
200
300
400
500
0
0.5 IOUT (A)
1.0
1.5
TIME (ns)
Figure 8. Saturation Curves 6
Figure 10 Rise/Fall Time (CL = 10,000pF)
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ML4823
SOFT START AND CURRENT LIMIT The ML4823 employs two current limits. When the voltage at ILIM/SD exceeds the ILIM REF threshold on ILIM REF, the outputs are immediately shut off and the cycle is terminated for the remainder of the oscillator period by resetting the RS flip flop. If the output current is rising quickly (usually due to transformer saturation) such that the voltage on pin 9 reaches 1.4V before the outputs have turned off, a soft start cycle is initiated. The soft start capacitor is discharged and outputs are held "off" until the voltage at SS reaches 1V, ensuring a complete soft start cycle. The duty cycle on start up is limited by limiting the output voltage of the error amplifier voltage to the voltage at the SS pin.
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ML4823
PHYSICAL DIMENSIONS
inches (millimeters)
Package: P16 16-Pin PDIP
0.740 - 0.760 (18.79 - 19.31) 16
PIN 1 ID
0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26)
0.02 MIN (0.50 MIN) (4 PLACES)
1 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN)
0.170 MAX (4.32 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.022 (0.40 - 0.56)
SEATING PLANE
0 - 15
0.008 - 0.012 (0.20 - 0.31)
Package: Q20 20-Pin PLCC
0.385 - 0.395 (9.78 - 10.03) 0.350 - 0.356 (8.89 - 9.04) 1 0.042 - 0.056 (1.07 - 1.42) 0.025 - 0.045 (0.63 - 1.14) (RADIUS)
0.042 - 0.048 (1.07 - 1.22)
6
PIN 1 ID
16
0.350 - 0.356 (8.89 - 9.04)
0.385 - 0.395 (9.78 - 10.03)
0.200 BSC (5.08 BSC)
0.290 - 0.330 (7.36 - 8.38)
11 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.165 - 0.180 (4.19 - 4.57) 0.146 - 0.156 (3.71 - 3.96) 0.009 - 0.011 (0.23 - 0.28) 0.100 - 0.110 (2.54 - 2.79)
0.013 - 0.021 (0.33 - 0.53) SEATING PLANE
8
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ML4823
PHYSICAL DIMENSIONS
inches (millimeters)
Package: S16W 16-Pin Wide SOIC
0.400 - 0.414 (10.16 - 10.52) 16
0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID
1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0 - 8
0.090 - 0.094 (2.28 - 2.39)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE
0.005 - 0.013 (0.13 - 0.33)
0.022 - 0.042 (0.56 - 1.07)
0.009 - 0.013 (0.22 - 0.33)
ORDERING INFORMATION
PART NUMBER ML4823CP ML4823CQ ML4823CS ML4823IQ ML4823IS ML4823MJ TEMPERATURE RANGE 0C to 70C 0C to 70C 0C to 70C -40C to 85C -40C to 85C -40C to 85C PACKAGE 16-Pin PDIP (P16) 20-Pin PLCC (Q20) 20-Pin Wide SOIC (S16W) 16-Pin PDIP (P16) 20-Pin PLCC (Q20) 16-Pin Wide SOIC (S16W)
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com
REV. 1.0 10/12/2000
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
(c) 2000 Fairchild Semiconductor Corporation
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